1. Field of the Invention
The invention relates generally to an apparatus for and method of suppressing formation of parasitic edge transistors near a field effect transistor being formed on a semiconductor substrate. More particularly, the invention relates to an apparatus and method of obtaining rounded top and bottom corners of a trench used to form the field effect transistor in order to reduce parasitic edge transistors near the field effect transistor.
2. Description of the Related Art
Various methods have been developed to isolate devices within integrated circuits. One of the methods is known as trench etch and refill. In this method, a trench is etched into a substrate and is filled with a chemical vapor deposition (CVD) oxide. The etched trench may be shallow (depth&lt;1 .mu.m), of moderate depth (1 .mu.m.ltoreq.depth.ltoreq.3 .mu.m), or deep and narrow (depth&gt;3 .mu.m and width&lt;2 .mu.m). Deep and narrow trenches refilled with CVD oxide are particularly useful for preventing latchup and for isolating n-channel from p-channel devices in CMOS circuits.
Fabrication of trenches, however produces parasitic edge transistors at the corners and edges of the trench sidewalls. Parasitic edge transistors are not desired because they increase the OFF current of the devices of the integrated circuit and increase the susceptibility to latchup. Parasitic edge transistors also turn on at a lower voltage than the active device, thereby causing a phenomenon known as a "subthreshold kink" in the drain current versus gate voltage (I.sub.D -V.sub.G) characteristic curve.
FIG. 1 shows a conventional deep-and-narrow isolation trench structure. A silicon substrate 50 is formed with trenches 20. Trenches 20 are filled with an oxide to isolate active devices from each other. A gate oxide 10 covers the substrate 50 and the oxide in the trenches 20. A gate polysilicon (poly) electrode 60 is on top of the gate oxide 10 and positioned over the substrate 50 to form an active device with the ends of the gate poly electrode 60 extending over a portion of the trenches 20.
The oxide 10 is formed with dimples in the trenches 20. The dimples are caused by overetching of a sacrificial oxide (sacox) prior to forming the gate oxide 10. When the gate oxide 10 and the gate poly electrode 60 are added, the poly recesses partially into the trenches 20.
The conventional structure, as shown in FIG. 1, forms parasitic edge transistors at the corners and edges of the trenches 20. The recessed portion of the gate poly electrode 60 acts as a gate electrode of the parasitic transistor and the portion of the gate oxide between the recessed portion and the side wall of the trench 20 acts as a gate oxide of the parasitic transistor.
Further problems occur due to a thinning of the gate oxide 10 at the corners and edges of the trenches 20 where the gate oxide 10 recesses into the trenches 20. Thinned gate oxide decreases reliability and increases the electric field strength at the trench corner and edge, thereby exacerbating the above discussed problem regarding parasitic transistors.
Another possible solution to reducing parasitic edge transistors is to dope the corner and edge regions of the trench sidewalls. By introducing dopants into the trench sidewalls, the parasitic edge transistors are shut off and the subthreshold kink in the Id versus Vg characteristic curve is suppressed to some extent.
FIGS. 2A-2C illustrate a conventional method for reducing parasitic edge transistors by doping the corner and edge regions of the trench sidewalls. A trench 20 is etched from a substrate 50, as shown in FIG. 2A. Subsequently, in FIG. 2B, ions 14 are implanted into the corners and edges 25 of the trench 20 using a method known as angle implantation. FIG. 2C illustrates the trench 20 after the step of angle implantation has been completed.
A disadvantage of the conventional method described above and illustrated in FIGS. 2A-2C is that angle implantation becomes extremely difficult for deep, narrow trenches and for very narrow trenches (width.ltoreq.0.5 .mu.m) with a high aspect ratio (aspect ratio is defined as the ratio of the height of the trench to its width).
FIGS. 3A-3C illustrate the relative difficulty of implanting ions into trenches with higher aspect ratios. FIG. 3A illustrates the easiest of the three geometries for ion implantation. Ion implantation is more difficult with the geometry of FIG. 3B and the most difficult the geometry of FIG. 3C. It is well known that the difficulty of ion implantation is a function of the incidence angle .alpha.. The larger the incidence angle .alpha., the easier the ion implantation.
In FIGS. 3A-3C, the incidence angle .alpha. is dependent on two independent variables--first, the width (or the aspect ratio) of the trenches and second, the thickness of the mask layer (t.sub.m, which can be up to 1 .mu.m). FIGS. 3B and 3C illustrate the effect of an increase in the thickness of the mask layer (t.sub.m), known as a shadowing effect, on the incidence angle .alpha..
Another disadvantage of the above-described conventional method is that the angle at which ion implantation is carried out needs to be adjusted in accordance with the trench width. Therefore, the wafer on which the IC devices are formed must be tilted so that a desired angle of incidence .alpha. is achieved with respect to one sidewall of the trench. Thereafter, the wafer must be rotated by 90.degree.0 three times, so that each sidewall of the trench can be implanted at the same desired angle of incidence .alpha..